The present invention generally relates to the preparation of semiconductor material substrates, especially silicon wafers, which are used in the manufacture of electronic components. More particularly, the present invention relates to a process for thermally treating or annealing a silicon wafer to reduce the concentration of agglomerated vacancy defects without substantially increasing the appearance of haze on the surface of the thermally treated silicon wafer.
Single crystal silicon wafers are commonly manufactured by a process which starts with the growth of a monocrystalline silicon ingot produced by the Czochralski (xe2x80x9cCzxe2x80x9d) method or the float-zone (FZ) method. The crystal ingot is typically sliced into wafers with a wire-saw, the wafers are flattened by lapping and chemically etched to remove mechanical damage and contamination. After being etched, the wafers are polished on one or both sides.
A polished wafer typically has undesirable defects (e.g., Crystal Originated Pits/Particles (COPs)) on the surface that were formed as the ingot cooled after solidification which are detectable by laser scatter inspection tools. Such defects arise, in part, due to the presence of an excess (i.e. a concentration above the solubility limit) of intrinsic point defects, which are known as vacancies and self-interstitials. Silicon crystals grown from a melt are typically grown with an excess of one or the other type of intrinsic point defect, either crystal lattice vacancies or silicon self-interstitials. It has been suggested that the type and initial concentration of these point defects in the silicon are determined at the time of solidification and, if these concentrations reach a level of critical supersaturation in the system and the mobility of the point defects is sufficiently high, a reaction, or an agglomeration event, will likely occur. Agglomerated intrinsic point defects in silicon can severely impact the yield potential of the material in the production of complex and highly integrated circuits. Examples of vacancy-type intrinsic point defects (hereinafter xe2x80x9cagglomerated vacancy defectsxe2x80x9d) include dislocations, surface defects, Flow Pattern Defects (FPDs), COPs, and oxidation induced stacking faults (OISF).
To date, there generally exists three main approaches to dealing with the problem of agglomerated intrinsic point defects. The first approach includes methods which focus on crystal pulling techniques in order to reduce the number density of agglomerated intrinsic point defects in the ingot. For example, it has been suggested that the number density of agglomerated defects can be reduced by (i) controlling v/Go to grow a crystal in which crystal lattice vacancies are the dominant intrinsic point defect, and (ii) influencing the nucleation rate of the agglomerated defects by altering (generally, by slowing down) the cooling rate of the silicon ingot from about 1100xc2x0 C. to about 1050xc2x0 C. during the crystal pulling process. While this approach reduces the number density of agglomerated defects, it does not prevent their formation and reducing the cooling rate decreases the throughput of the crystal growth apparatus thereby increasing the cost of producing wafers.
A second approach to dealing with the problem of agglomerated vacancy defects is the epitaxial deposition of a thin crystalline layer of silicon on the surface of a single crystal silicon wafer. This process provides a single crystal silicon wafer having a surface which is substantially free of agglomerated vacancy defects; however, the cost of the wafer substantially increases.
The third approach to dealing with the problem of agglomerated vacancy defects includes methods which focus on the dissolution or annihilation of the vacancy defects subsequent to their formation. Generally, this is achieved by using high temperature heat treatments of silicon wafers. The reduction of COPs is of particular interest because Gate Oxide Integrity failures correlate to the concentration of COPs on the wafer surface. D. Graf, M. Suhren, U. Schmilke, A. Ehlert, W. v. Ammon and P. Wagner., J. Electrochem. Soc. 1998, 145, 275; M. Tamatsuka, T. Sasaki, K. Hagimoto and G. A. Rozgonyi, Proc. 6th. Int. Symp. On Ultralarge Scale Integration Science and Technology xe2x80x9cULSI Science and Technology/1997,xe2x80x9d The Electrochemical Society 1997, PV97-3, p. 183; and T. Abe, Electrochem. Soc. Proc. 1998, PV98-1, 157; N. Adachi, T. Hisatomi, M. Sano, H. Tsuya, J. Electrochem. Soc. 2000, 147, 350. COPs within an ingot or wafer are octahedral voids. At the surface of a wafer, the COPs appear as pits with silicon dioxide covered walls and are typically about 50-300 nm wide and can be up to about 300 nm deep. It is presently believed that heat treating a wafer in certain ambients increases the migration of silicon atoms to the COPs which decreases the depth of the COPs until they appear as shallow dish-like depressions that are not usually detected by automated inspection tools.
Previously disclosed heat treatments, or thermal annealing processes, include long term annealing in a hydrogen atmosphere (e.g., longer than about 30 minutes) which produces virtually COP-free surfaces, however, the duration is cost prohibitive. D. Graf, U. Lambert M. Brohl, A. Ehlert, R. Wahlich, P. Wagner., J. Electrochem. Soc. 1995, 142, 3189. Short term hydrogen annealing processes (less than about 5 minutes) do not sufficiently annihilate COPs. A significant drawback to annealing a silicon wafer in a hydrogen ambient (short or long term) is the significant increase in haze on the wafer surface (e.g., to levels greater than about 1.2 ppm measured by a SURFSCAN 6220 laser scatter inspection tool or to levels greater than about 0.2 ppm measured by a SURESCAN SP1 laser scatter inspection tool which are available from KLA-Tencor of San Jose, Calif., U.S.A.). Annealing a wafer in an argon ambient has also been disclosed. D. Graf, M. Suhren, U. Lambert, R. Schmolke, A. Ehlert, W. v. Ammon and P. Wagner, Electrochem. Soc. Proc. 1996, 96-13, 117; Iida, W. Kusaki, M. Tamatsura, E. Iino, M. Kimura and S. Murasoka, Electrochem. Soc. Proc. 1999, 99-1, 449. Although annealing in argon annihilates COPs at the surface and near-surface (e.g., extending inward from the surface about 5000 nm) of the wafer more effectively than an H2 ambient, it results in considerably higher haze levels than that of H2 annealing. Short high temperature annealing cycles (less than about 5 minutes) in a mixture of H2 and Ar have also been attempted for surface COP annihilation and GOI improvement with similar increases in the haze. T. Abe, Electrochem. Soc. Proc. 1998, 98-1, 157; M. Tamatsuka, N. Kobayashi, S. Tobe, and T. Masiu, Electrochem. Soc Proc, 1999, 99-1, 456); D. Grxc3xa4f, M. Suhren, U. Lambert, R. Schmolke, A. Ehlert, W. v. Ammon, and P. Wagner, Electrochem. Soc. Proc. 1996, 96-13, 117; and W. Iida, M. Kusaki, E. Tamatsura, M. K. Iino S. Muraoka, Electrochem. Soc. Proc. 1999, 99-1, 449.
In view of these shortcomings, a need continues to exist for a low-cost method to annihilate or reduce the size of silicon wafer surface and/or sub-surface defects without the formation of excessive haze.
Among the objects of the present invention, therefore, is the provision of a low-cost process for the manufacture of silicon wafers to reduce the size of silicon wafer surface and/or sub-surface defects without the formation of excessive haze.
Briefly, therefore, the present invention is directed to a process for manufacturing a silicon wafer sliced from a single crystal ingot, the silicon wafer having a front surface, a back surface, an imaginary central plane between the front and back surfaces, and exposed agglomerated vacancy defects on the front surface, the process comprising:
a. cleaning the front surface of the silicon wafer at a temperature of at least about 1100xc2x0 C. by exposing the front surface to a cleaning ambient comprising H2, HF gas, or HCl gas to remove silicon oxide from the front surface; and
b. exposing the cleaned front surface of the silicon wafer at a temperature of at least about 1100xc2x0 C. to a vacuum or an annealing ambient that removes less than about 0.1 nm/mm of silicon from the cleaned front surface of the silicon wafer to facilitate the migration of silicon atoms to the exposed agglomerated vacancy defects thereby reducing the size of the exposed agglomerated vacancy defects.
This invention is also directed to a process for manufacturing a silicon wafer comprising:
a. growing a silicon ingot having a {100} crystallographic orientation and a density of agglomerated vacancy defects of about 1xc3x97103/cm3 to about 1xc3x97107/cm3;
b. slicing the silicon wafer from the silicon ingot off the [100] direction by about 1 minute to about 13 minutes off the x-axis and about 1 minute to about 13 minutes off the y-axis, the silicon wafer having a front surface, back surface, the front surface comprising exposed agglomerated vacancy defects;
c. heating the silicon wafer to an annealing temperature of at least about 1100xc2x0 C. at an average rate of about 1xc2x0 C./sec to about 30xc2x0 C./sec;
d. cleaning the front surface of the silicon wafer at the annealing temperature by exposing the front surface to a cleaning ambient consisting essentially of H2 gas for about 15 seconds to about 60 seconds to remove silicon oxide from the front surface;
e. exposing the cleaned front surface of the silicon wafer at the annealing temperature to an annealing ambient consisting essentially of Ar for about 10 seconds to about 5 minutes; and
f. cooling the silicon wafer from the annealing temperature to a temperature below about 900xc2x0 C. at an average rate of about 1xc2x0 C./sec to about 30xc2x0 C./sec while exposing the front surface of the silicon wafer to the annealing ambient after step e.
The invention is also directed to a process for manufacturing a silicon wafer sliced from a single crystal ingot, the silicon wafer having a front surface, a back surface, and an imaginary central plane between the front and back surfaces, the process comprising:
a. cleaning the front surface of the silicon wafer at a temperature of at least about 1100xc2x0 C. by exposing the front surface to a cleaning ambient comprising H2, HF gas, or HOI gas to remove silicon oxide from the front surface, the cleaned front surface having more than about 0.5 light point defects per cm2; and
b. exposing the cleaned front surface of the silicon wafer at a temperature of at least about 1100xc2x0 C. to a vacuum or an annealing ambient that removes less than about 0.1 nm/mm of silicon from the cleaned front surface of the silicon wafer to reduce the concentration of light point defects on the front surface of the silicon wafer by at least about 50%.
The invention is also directed to a process for manufacturing a silicon wafer sliced from a single crystal ingot, the silicon wafer having a front surface, a back surface, an imaginary central plane between the front and back surfaces, and agglomerated vacancy defects dispersed throughout the volume of the wafer, the process comprising:
a. cleaning the front surface of the silicon wafer at a temperature of at least about 1100xc2x0 C. by exposing the front surface to a cleaning ambient comprising H2, HF gas, or HCl gas to remove silicon oxide from the front surface, the agglomerated vacancy defects in the cleaned silicon wafer having a width that is between about 50 nm and about 300 nm; and
b. exposing the cleaned front surface of the silicon wafer at a temperature of at least about 1100xc2x0 C. to a vacuum or an annealing ambient that removes less than about 0.1 nm/mm of silicon from the cleaned front surface of the silicon wafer for a duration sufficient to create a stratum extending from the front surface inward a distance of about 5 nm to about 500 nm in which the width of the agglomerated vacancy defects is reduced.
The invention is also directed to a process for manufacturing a silicon on insulator structure, the silicon on insulator structure comprising a handle wafer having a back surface and a front surface, a single crystal silicon device layer having a back surface and a front surface, an insulating layer between the front surface handle wafer and the back surface of the device layer and exposed agglomerated vacancy defects on the front surface of the device layer, the process comprising:
a. cleaning the front surface of the device layer at a temperature of at least about 1100xc2x0 C. by exposing the front surface of the device layer to a cleaning ambient comprising H2, HF gas, or HCl gas to remove silicon oxide from the front surface of the device layer; and
b. exposing the cleaned front surface of the device layer at a temperature of at least about 1100xc2x0 C. to a vacuum or an annealing ambient that removes less than about 0.1 nm/mm of silicon from the front surface of the device layer to facilitate the migration of silicon atoms to the exposed agglomerated vacancy defects thereby reducing the size of the exposed agglomerated vacancy defects.
This invention is also directed to a single crystal silicon wafer having two generally parallel surfaces, one of which is the front surface of the wafer and the other of which is the back surface of the wafer, an imaginary central plane between the front and back surfaces, a circumferential edge joining the front and back surfaces, and agglomerated vacancy defects dispersed throughout the volume of the wafer, the wafer being characterized in that:
the silicon wafer has a density of agglomerated vacancy defects of between about 1xc3x97103 defects/cm3 and about 1xc3x97107 defects/cm3 between the imaginary central plane and a stratum extending from the front surface inward a distance Ds, and a density of agglomerated vacancy defects in the stratum that is less than the density of agglomerated vacancy defects between the imaginary central plane and the stratum;
the front surface of the silicon wafer has a concentration of light point defects that is less than about 3 LPDs/cm2; and
the front surface of the silicon wafer has a degree of haze which allows the detection of LPDs less than about 0.21 xcexcm LSE.
The present invention is also directed to a silicon on insulator structure having two generally parallel surfaces, one of which is the front surface of the structure and the other of which is the back surface of the structure and a circumferential edge joining the front and back surfaces of the structure, the structure comprising:
a. a single crystal silicon base layer having two generally parallel borders, one of which is the top border and the other of which is the bottom border which coincides with the back surface of the silicon on insulator structure, and an imaginary central plane between the borders;
b. a single crystal silicon device layer having two generally parallel boundaries, one of which is the upper boundary which coincides with the front surface of the structure and the other of which is the lower boundary;
c. an insulating layer between the top border of the base layer and the lower boundary of the device layer;
d. a first reduced defect stratum comprising agglomerated vacancy defects ranging in width from about 50 nm to about 300 nm dispersed throughout its volume at a density less than about 1xc3x97103 defects/cm3, the first reduced defect stratum being generally parallel to the back surface of the structure, and having a thickness Ds1 and being located in the device layer or the base layer; and
e. a first bulk stratum comprising agglomerated vacancy defects ranging in width from about 50 nm to about 300 nm dispersed throughout is volume at a density greater than about 1xc3x97103 defects/cm3, the first bulk stratum being generally parallel to the back surface of the structure and being located in the device layer or the base layer.
Other objects and features of this invention will be in part apparent and in part pointed out hereinafter.